Solutions [Chip specifications]
The IPQ8064 is an internet processor for carrier gateway and smart retail router. The IPQ8064 includes a powerful dual-core SMP Krait CPU at 1.4 GHz with an ARM-v7-compliant instruction set. Each Krait CPU includes a 128-bit SIMD DSP, referred to as VeNum. The CPU system is supported by 1 MByte of L2 cache as well as 16 KiB L1 I-Cache and 16 KiB L1 D-Cache.
The IPQ8064 also includes a network accelerator with an aggregate throughput capacity of 5 Gbps. This network accelerator is referred to as the Networking Subsystem (NSS). The NSS consists of two programmable, multithreaded, network accelerator engines. Each network accelerator engine supports 12 threads of execution. The function of each thread is determined by firmware (FW) provided by Qualcomm Atheros. The NSS architecture allows the threads to operate in parallel. NSS functions include L2/L3 routing/bridging, Samba acceleration, LRO/TSO offload, connectivity acceleration, as well as traffic management.
The IPQ8064 typically runs an OpenWRT Linux IP stack on the Dual Core SMP Krait, while the NSS accelerates networking traffic (fast path). The NSS operates under full control of the Linux stack. Rules in the NSS are set by the Linux stack. Networking packets that do not match these rules are passed on to the Linux stack through an exception handling mechanism in the NSS.
To support a large variety of platforms, the IPQ8064 is equipped with several high speed Serdes and general purpose interfaces. These include:
4×GMACs, configurable as:
3×PCIe 2.0 (root complex)
2×USB3 (host and device mode)
2×Transport Stream Interface (TSIF)
6×general-purpose serial interfaces (GSBI), configurable as SPI, UART, I 2 C, UIM.
Complementary blocks within the IPQ8064 include:
Wireless video transmission Wi-Fi 5 Wi-Fi 6 Wi-Fi 6E Wi-Fi 7 OEM ODM JDM
MU-MIMO AP CPE QSDK openwrt
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