11AX IPQ8074 IPQ8072 YBT8074 YBT8072 Core board

YBT8074:IPQ8074+QCN5024*3+QCA8075+AQR112C

YBT8072:IPQ8072+QCN5024*2+QCA8072+AQR112C

Core board

1、Introduction

IPQ8074 is an SoC for 11ax Wi-Fi Access Points, Retail Routers and Carrier Gateways. The chip consists of a Wi-Fi subsystem, a networking subsystem and a CPU subsystem.

1.1 Functional block diagram

1.2 Wi-Fi subsystem

The Wi-Fi subsystem supports IEEE802.11ax. The IPQ8074 supports dual band dual current (DBDC) operation. 12 antenna chains operate in a two radio configuration as 8×8 in 5 GHz and 4×4 in 2.4 GHz.

The Wi-Fi PHY rates equate to 5950 Mbps, 4800 Mbps for 5 GHz and 1150 Mbps for 2.4 GHz, enabling an AX6000 product.

1.3 Networking subsystem

The networking subsystem is a high performance high throughput programmable offload engine to the networking stack that runs on the Host CPU subsystem. It interfaces to 3 Ethernet SerDes to connect to external multi-GbE PHYs. Two of the three SerDes support up to 10GbE PHY (either USXGMII, XFI, SGMII or SGMII+) while the third SerDes runs in either PSGMII, QSGMII or SGMII mode to connect to QCA8075 (5 port GbE PHY array) or QCA803x (single port GbE PHY).

The networking subsystem is capable of classifying incoming packets at an aggregate throughput rate of 25 Gbps, 37.5 million packets per second (Mpps) for 64Byte packets. This high performance ingress packet engine makes IPQ8074 very well suited to deliver Quality of Service (QoS) for carrier gateway applications to guarantee zero packet loss for paid services like voice and video.

The networking subsystem performs standard routing/bridging within the WAN/LAN Ethernet ports at a peak rate of 37.5 Mpps. Advanced features including tunneling and de/fragmentation are performed by a networking processing unit (NPU) that consists of dual 12 threaded programmable engines (UBI32 cores), each running at 1.5 GHz for up to 2.2 Mpps throughput.

IPQ8074 contains an in line security engine with AES 128/256, SHA1-96, 128, 256, and 512 and 3DES for up to 5 Gbps throughput.

 

1.4 CPU subsystem

The CPU subsystem consists of quad ARM Cortex A53s @ 2 GHz, with 64 bit ISA v8 instruction set. The I$/D$ sizes of core are 32kB, while the L2$ is 512kB. Each A53 core has a 64-bit Floating Point/NEON DSP extension that could be used for enhanced audio/voice/video processing.

1.5 Interfaces and power management

IPQ8074 comes with a large variety of interfaces to enable various platform configurations. It has dual PCIe gen2, dual USB3.0, multiple serial IOs selectable between SPI/I2C/UART, Dual SDIO for eMMC and SD card, I2S/PCM/Display Interfaces 16/32 bits DDR3L/4 up to 2133 MT/s, parallel NAND, serial NOR, and Wi-Fi/IOT coexistence interfaces for up to 4 radios.

IPQ8074 comes with advanced power management for lowest active and standby power consumption, making it extremely valuable for carrier gateway and Enterprise AP power over Ethernet (PoE) applications. A companion PMIC PMP8074 is used to optimally manage active/standby power.

1.6 IPQ8074 features

1.6.1 Wi-Fi subsystem

  • 5 GHz antenna configuration
  1. 8×8/8s-80MHz or 4×4/4s-80+80MHz
  • 2.4 GHz antenna configuration
  1. 4×4/4s-40MHz
  • Twelve IQ transmit pairs and twelve IQ receive pairs to external QCN50xx
  • 802.11ac mode
  1. PHY rate: 3466 Mbps (5 GHz) and 800 Mbps (2.4 GHz)
  2. 5 GHz: SU-MIMO (8ss, 1 user) and MU-MIMO (8ss, 4 users)
  3. 2.4 GHz: SU-MIMO (4ss, 1 user) and MU-MIMO (4ss, 4 users)
  4. Explicit beamforming
  5. 3.2 µs Symbol Duration; 0.4 µs and 0.8 µs GI 802.11ax mode
  6. PHY rate: 4800 Mbps (5 GHz) and 1150 Mbps (2.4 GHz)
  7. 5 GHz: SU-MIMO (8ss, 1 user), DL MU-MIMO (8ss, 8 user), DL-OFDMA (8 users)
  8. 2.4 GHz: SU-MIMO (4ss, 1 user), DL MU-MIMO (4ss, 4 user), DL-OFDMA (8 users)
  9. Explicit beamforming
  10. 12.8 µs Symbol Duration; 0.8 µs, 1.6 µs, or 3.2 µs GI Legacy 11a/b/g/n Radio Control interfaces, including Smart Antenna interface to manage external antenna switch
  • Legacy 11a/b/g/n
  • Radio Control interfaces, including Smart Antenna interface to manage external antenna switch

1.6.2 Networking subsystem

  • 3 SerDes for external Ethernet PHYs
  1. Dual up to 10.3125G Ethernet SerDes ports for external 10/5/2.5/1GbE PHYs. Each SerDes can operate in XFI, USXGMII, SGMII+ or SGMII mode
  2. Single up to 6.25G Ethernet SerDes for external 5 or 4 ports GbE PHY array or single
  • GbE PHY Packet Acceleration
  1. Packet Processing Engine (PPE) for standard 5-tuple routing/bridging of IPv4 and IPv6 packets with ingress capacity of 37.5M packet per second (Mpps) and egress capacity of up to 10 Mpps per port

    – Flexible VLAN assignment and translation on ingress, including filtering, double tag, single tag, untag, priority tag

    – Classification based on L2/L3/L4 and User Defined fields; actions like policing, QoS Marking, en-queue, forwarding, and so forth

    – Flow based routing/bridging/NAT; IPv4 unicast routing and NAT, IPv6 unicast routing, PPPoE IPMC bridging

    – MAC table for Bridge learning and aging, Station Movement control, L2 multicast, Spanning tree, Link aggregation, Egress VLAN filtering, PPPoE

    – Egress Queues:

    • 256 unicast and 44 multicast queues

    • PCP, DSCP, Flow, Classifier based Priority

    • Classifier based policer with two rate, three color meter, marker

    • Ingress scheduling, shaping

    • WRED lite with color aware dynamic, and static threshold

  2. 2-level Scheduler, 3-level Shaper with CIR, EIR rate control (HTB lite) Dual Core Twelve-Threaded network processing unit (NPU) Ubi32 @ 1.5 GHz for up to 2.2 Mpps throughput.
  3. Wi-Fi driver offload on NPU (optional)
  4. Up to 64k flows between PPE/NPU/CPU
  5. 4 level QoS between pipelines
  • Security
  1. In line security engine– Up to 5 Gbps– AES 128, 256– SHA 1-96, 128, 256, 512– 3DES 1-96, MD5-96– CCM operation
  2. 4 OTP keys for multi root revocation
  3. SDIO in line crypto
  4. Secure execution environment
  5. ARM Trustzone

1.6.3 CPU subsystem

  • Quad ARM Cortex A53 at 2 GHz, 64bits ISA v8 instruction set, 18.4k DMIPS
  • 32kB/32kB I$/D$ and 512kB L2$
  • Floating Point & NEON SIMD DSP for each core
  • Supports crypto instruction extensions

 

1.6.4 Peripherals/interfaces

  • Dual PCIe-gen2
  • Dual USB3.0
  • Multiple programmable serial interface for SPI, UART or I2C
  • I2S, PCM, and TDMA
  • Parallel NAND, eMMC and Display Interface
  • Serial NOR
  • SD-card
  • 16 or 32 bits DDR3L at 1866 MT/s or DDR4 at 2133 MT/s

 

1.6.5 Power management

  • Advanced Power Management for lowest active and stand-by power consumption
  • Interface to external PMIC (PMP8074)

 

1.6.6 Platform extension options

  • BT/BLE/15.4 companion chip through SPI/UART
  • LTE-WAN through PCIe (or USB)
  • 802.11ad through PCIe
  • Wi-Fi radio through PCIe
  • SLIC through PCM
  • Audio Tx/Rx through I2S/TDMA
  • Display through QPIC port
  • DECT through PCM/SPI
  • Storage through USB3.0

 

1.6.7 Package

  • 21 mm × 21 mm 772-pin FCBGA package
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